1. Technical Field
The present invention relates to the technical field of integrated circuit manufacturing process, and more especially, to a method for making SONOS memory.
2. Description of Related Art
With the advanced IC manufacturing process and decreased line width of photolithography technology, the area of semiconductor device is becoming smaller and smaller. The semiconductor has evolved from common single function device to integrated high-density multi-function IC (integrated circuit); from the initial IC to LSI (large scale integrated circuit), VLSI (very-large scale integrated circuit), even ULSI (ultra-large scale integrated circuit) at present, the chip area keeps reducing and functions become more powerful. Considering the restrictions of many unfavorable factors such as the complexity of technical research and development, long-term performance and expensive costs, chip designers and manufacturers will pay more attention to the problem of how to further improve integrated density on the basis of the existing technology, reduce the chip area and get chips as many as possible from one silicon wafer so as to upgrade the overall interests.
Among various semiconductor technologies, wet etching technology plays a key role in critical steps such as dual gate oxide etching and surface cleaning due to the plasma damage issue and high selectivity requirement. However, the technology has an inherent problem: that is isotropy etch, which indicates that lateral etching concurs along with the proceeding of longitudinal etching and leads to the reliability issue, which is intolerable for devices. Therefore, how to prevent lateral etching of wet etching becomes the problem requiring a solution in the industry.
SONOS is an abbreviation word, which represents a film stack structure of five different materials: silicon, silicon oxide, silicon oxynitride, silicon oxide and polysilicon (from top to bottom). The film stack is one of composite gate structures and is widely used in advanced flash technology. SONOS has very high compatibility with standard CMOS technology, and is provided with numerous advantages such as high durability, low power and high radiation resistance. Moreover, comparing with other embedded non-volatile memories, SONOS provides more stable solutions easier to manufacture with higher performance-price ratio. This technology is widely adopted in industry due to the compact structure and property of downward extension.
Refer to FIG. 1˜FIG. 6 for the existing process flow: FIG. 1: deposit the first oxide layer 12, silicon oxynitride 13 and the second oxide layer 14 on silicon underlayer 11 in sequence, set device isolation area 15 in the silicon underlayer 11; FIG. 2: coat a layer of photoresist on the second oxide layer 14, and form a photoresist pattern 16 by exposing; FIG. 3: remove the second oxide layer 14 and the silicon oxynitride layer 13 un-protected by the photoresist pattern 16 via dry etching process in order to avoid plasma induce damage; FIG. 4: remove the first oxide layer 12 un-protected by the photoresist pattern 16 by means of wet etching; FIG. 5: remove the photoresist pattern 16 and grow gate oxide layer 17; FIG. 6: deposit polysilicon 18, perform photo and etch, to form the device structure of SONOS memory. In FIG. 4, during removing the first oxide layer 12 un-protected by the photoresist by means of wet etching, the silicon oxynitride layer 13 and the second oxide layer 14 nearby would be damaged due to isotropy character of wet etch, while the stability of memory storage performance will be downgraded if the second oxide layer 14 as the top oxide layer of memory is partly etched, further leading to reduced conforming rate of device.